The ConFab 2012 Conference
Managing the New Economics
of Semiconductor Manufacturing
Monday, June 4
8:00AM - 8:45AM - Keynote Speaker
The Next Transformation of the Semiconductor Industry
John Chen
Vice President of Technology and Foundry Operations
Nvidia
In a talk titled “The Next Transformation of the Semiconductor Industry,” John Chen will present the concept of “virtual IDM” as a way for foundries, fabless and OSATs to collaborate to solve the new challenges in technology, manufacturing and business.
John Y. Chen has been in the semiconductor industry for 35 years ranging from IDM to Foundry to Fabless. He currently serves as the vice president of technology and foundry management at NVIDIA Corporation. Prior to that, Dr. Chen held senior executive positions at FlexICs Inc., TSMC, WaferTech LLC, and Cypress Corporation. These positions contributed to his broad industry experience and include Senior VP of engineering, VP of R&D, VP of operations and VP of business development. Earlier in his carrier at Hughes Research Lab and Xerox Palo Alto Research Center, he has made contributions in CMOS with more than 100 research papers and a book published by Prentice Hall. He was elected to the IEEE Fellow in 1992 for “leadership in and contributions to CMOS device and process technology”.
Dr. Chen holds a B.S. in E.E. from National Taiwan University, an M.S. in E.E. from University of Maine, a Ph.D. in E.E. from UCLA, and a Master degree from the UCLA Executive Engineering Management Program. He was a Technical Advisor for ITRI, Taiwan. He now serves on few boards in the industry and academia.
8:45AM - 11:00AM
Session #1: The Economic Outlook for the Semiconductor Industry
The worldwide chip market is expected to suffer a slow year in 2012, as global economic prospects remaining uncertain. Semiconductor industry revenue in 2012 is expected to reach $323.2 billion, up a slight 3.3 percent from last year’s revenue of $312.8 billion. However, although spending on fab equipment is expected to drop in the first half of 2012, it is then expected to sharply increase in the second half of the year. This session will provide a look forward with an eye on what is driving the semiconductor market, and also look at the main challenges facing the maturing semiconductor industry.
Speakers:
Jackie Sturm
Vice President of TMG, General Manager of Global Sourcing and Procurement
Intel
Global economic uncertainty clouds the prospects for the semiconductor industry. However, the aggregated, popular indicators mask the bright, growth stories and opportunities. We believe growth will be fueled by emerging market, innovative devices for consumers, and business refresh cycles. What this means for the semiconductor industry, for us as well as our materials suppliers and equipment suppliers, is opportunity.
Jackie Sturm has been at Intel since 1993 and in that time has held various positions including VP of Finance, for Technology and Manufacturing and NAND Systems Group, Intel Capital, New Business Group and Intel Communications Group. Prior to Intel, she worked for Hewlett Packard and Apple Computer.
Beating the Silicon Cycle
Dan Hutcheson
CEO and Chairman
VLSI Research
Prevailing over the Silicon Cycle is one of the biggest issues companies face. The industry has violent swings that affect every part of the supply chain. Worse, they tend to be unpredictable. The companies that beat the cycle do so by optimally balancing reacting with planning. This presentation covers how this is done while covering the near-term outlook for the industry.
Dan is CEO and Chairman of VLSI Research and weSRCH.com. He is a well-known visionary, helping companies make businesses out of technology for over thirty years and is arguably best known for his many predictions of strategic industry infrastructure shifts. Dan is a senior member of the IEEE and a recipient of SEMI’s Bob Graham Award for outstanding contributions in marketing. He has authored numerous publications including two invited articles for Scientific American. His pro bono work has included serving as an advisor on innovation to the White House Council of Economic Advisors in the Clinton Administration, teaching invited courses on Manufacturing Economics and The Economics of the Internet at Stanford University, and serving on the Board of Advisors to the Extension School at UC Berkeley.
The Economic Outlook for the Semiconductor Industry
Jim Feldhan
President
Semico
Mr. Feldhan's presentation will provide Semico's World Economic Outlook and Semico’s Semiconductor market forecast. The presentation will focus on the end applications and their impact on the semiconductor market. Feldhan will address the wafer production opportunities created by the driving market applications.
Jim Feldhan founded Semico Research in 1994. A 30+ year veteran of the semiconductor industry, he brings his management, forecasting and modeling expertise to Semico, along with a reputation of quality research. Jim designed and developed the research methodologies and report structures, which are the basis for Semico’s Custom Research and Portfolio Services. Jim also develops Semico’s Inflection Point Indicator and Semico’s overall economic outlook as well as performing various semiconductor consulting and forecasting. With a focus on quality.
Mr. Feldhan also held various management, marketing and manufacturing positions at GTE Microcircuits and Greyhound/Dial Corporation. Jim received a BS in Business with a minor in Chemistry from the University of Arizona and a MS in Marketing focusing on quantitative statistics and market research from the University of Arizona.
1:45PM - 3:15PM
Session #2: Technology Trends in Semiconductor Manufacturing
Smaller features, more complex device structures and the integration of more new materials all lie on the road ahead for most chip makers. The transition to 450mm wafer also looms. In this session, presenters will review leading challenges, various possible solutions, and discuss how the industry is addressing the high costs of advanced R&D.
Speakers:
It’s a small world
An Steegan
SVP for integration
IMEC
Chip scaling will go on for the foreseeable future, enabling new product with more compute power, more memory, faster on chip communication…Admittedly, there are technical obstacles, and some of them are formidable. But history shows that, with time and effort, this kind of challenges can be overcome. Sometimes with a lot of hard engineering, sometimes with cutting-edge innovation, sometimes involving delays and setbacks. But in the end, we always succeed. Established technologies need to be refined, and new architectures, new materials and new processing techniques explored and developed. As each successive technology generation is more complex than the previous one, more and more, collaborative R&D will become indispensable. This allows companies to share the risk and cost of this complex research.
Dr. An Steegen joined IMEC as Senior Vice President Process Technology Development in December 2010. In this role, she has the responsibility for the technical leadership and execution of IMEC’s CORE Program activities in the areas of devices, process, lithography and design and CMORE activities such as MEMS, Power, Sensors and Photonics. These leadership technologies serve as the foundation of IMEC’s successful growth and R&D leadership position in a wide variety of market segments.
Dr. An Steegen holds a Ph.D in Material Science and Electrical Engineering from the Catholic University of Leuven, KUL, in collaboration with the Interuniversity Microelectronics Center, IMEC, in Belgium. Throughout the years, Dr. Steegen has published more than 30 technical papers and she holds many patents in the field of semiconductor development. She joined IBM Semiconductor R&D in Fishkill, NY, in 2001, where she was the director of the Bulk CMOS Technology Development division until 2010. In that position, she served as the host executive in charge of IBM’s logic International Semiconductor Development Alliance and was responsible for establishing strong collaborative partnerships in innovation and manufacturing as measured by power/performance, defect density and cost/complexity.
Thomas Jefferson
G450 Consortium
Increasing wafer size has historically been a successful strategy to offset rising costs of leading-edge semiconductor manufacturing. G450C (Global 450mm Consortium) is a New York based public-private partnership program first announced in September of 2011 with participation and contributions from 5 major device makers and the State of New York. The goal is to develop a cost-effective test wafer fabrication infrastructure, equipment demonstrations & high-volume tools to enable a coordinated industry transition to 450mm wafers. The activities will be primarily located at The College of Nanoscale Science and Engineering (CNSE) in Albany , NY. G450C will help enable 450mm equipment development by providing bare and processed silicon, and metrology capabilities, with a goal of demonstration of unit-process capability and equipment reliability to support device maker 450m pilot line startups, with ultimate use of the capabilities established at CNSE for joint development activities and support of a comprehensive industry ecosystem. An overview of current 450mm landscape and industry readiness will be provided, along with a look-ahead of G450C plans and activities.
Tom Jefferson is the Program Coordination Manager of G450C, on assignment from Intel Corporation. Prior to his G450C assignment, he led all aspects of the ISMI 450mm transition planning effort. Jefferson has held various managerial and technical positions in the areas of factory automation, factory integration, systems engineering, wafer size conversion, industrial engineering, and material handling. He is formally the co-chair of the ITRS Factory Integration technical working group, and a former member of the ASMC technical committee. Jefferson holds a BS in industrial engineering from the Rochester Institute of Technology (RIT). He is the author of 20+ publications in his areas of technical expertise.
Naoya Hayashi
Research Fellow, Electronic Device Operations
Dai Nippon Printing Co., Ltd.
For more than 30 years at DNP, Naoya Hayashi has been responsible for development of photomask technologies, such as electron beam exposure systems, resist materials and processes, phase-shifting materials, and NGL masks for EUV and nanoimprint. He is the first and the only Research Fellow of DNP, an honor bestowed in 2007, and is the author and/or the co-author of more than 130 papers. He became a SPIE Fellow sin 2011. He joined Dai Nippon Printing Co.,Ltd (DNP) in 1977. He received his B.S. degree in Applied Chemistry, and M.S. degree in Electric Chemistry from Tokyo Institute of Technology, Tokyo, Japan.
EUV Lithography Manufacturing Introduction: Infrastructure Readiness
Stefan Wurm
Director of Lithography
Sematech
Extreme Ultraviolet Lithography (EUVL) has been in development for about a quarter century and is now getting ready for prime time with the first production tools expected to ship by year end 2012 and high volume manufacturing (HVM) ramp-up expected to start in 2014. The EUVL infrastructure to support the ongoing pilot line introduction is largely in place but productivity and cost remain a challenge for the HVM ramp-up. There is still a significant EUV source performance gap that must be closed. Resist materials to support the 22 nm half-pitch requirements are available with acceptable sensitivity and with some help from post processing also can meet the line width roughness requirements for memory products; contact hole resist performance still needs to improve. For EUV masks the main technical challenges remain the availability of defect free masks and of critical mask tools such as for defect review and inspection. EUV blank defects have been reduced to a level that can support memory products but further improvements are needed to meet logic defect requirements. Ramping up mask blank volume at yield to support the expected mask demand in 2014/15 is a challenge the industry must address for EUVL HVM introduction to be successful.
Dr. Stefan Wurm is Director of Lithography at SEMATECH, where he works as a GLOBALFOUNDRIES assignee. He has more than 20 years of industry and R&D experience and has held technical and management positions in research and development at AMD, Siemens Semiconductor Group, Infineon, Qimonda, and SEMATECH. He was first assigned to SEMATECH in the late 1990s to the International 300 mm Initiative (I300I), where he was responsible for 300 mm metrology tool equipment demonstrations.
Prior to his previous assignment as associate director of Lithography at SEMATECH, he served four years as SEMATECH’s extreme ultraviolet (EUV) program manager, where he has been instrumental in shaping and directing the SEMATECH EUV program which provides worldwide EUV infrastructure capabilities and technology learning to SEMATECH members. Dr. Wurm holds a doctorate in natural sciences from the Technische Universität München, Germany.
Tuesday, June 5th
8:00AM - 8:45AM Keynote Speaker
Smart Society, the Sensing Era and Signal Chain
Ali Sebt
CEO
Renesas Electronics America
This talk titled “Smart Society, the Sensing Era and Signal Chain,” Ali Sebt will address how we as an industry need to support this smart society and help it grow by focusing on the complete signal chain – from analog to digital to low power to the software intelligence – to develop connected, low-power-foundation devices that will shape the next generation of connectivity for a smarter world.
As President and Chief Executive Officer (CEO) at Renesas Electronics America Inc, Ali Sebt is responsible for Renesas’ overall business operations in the Americas market, including the worldwide development and support of all Americas-based customers and channel partners.
Most recently, Mr. Sebt was the Chief Operating Officer (COO) where he was responsible for overall business development, sales, marketing and engineering operations of the company’s Automotive, Communications & Computing, and Consumer & Industrial Business Units, the Planning and Operations Group, and Renesas Canada.
Prior to COO, Mr. Sebt was the Vice President of the Consumer & Industrial Business Unit and was responsible for overall business development, sales, marketing and engineering operations for microcontrollers and analog and power devices in the Americas. And previously, he was the Vice President of the System LSI Business Unit at Renesas Technology America, where he grew the company’s microcontroller market share in the Americas from fifth place to second place.
Mr. Sebt joined Renesas Technology America (formerly Hitachi Semiconductor America) in 1991 and held a number of successive management and executive positions. Previous to Renesas Technology America, Mr. Sebt’s positions included marketing manager for ASIC in-circuit emulators at Quickturn Design Systems, product marketing engineer for ASICs at Toshiba America, and applications engineer and product engineer at AMD and Monolithic Memories, Inc., responsible for programmable logic devices and field programmable gate arrays (FPGAs).
8:45AM - 10:15AM
Session #3: The Foundry-Fabless Supply Chain
Many semiconductor companies have adopted a fabless or “asset-lite” models for fabricating the chips they design. The most successful have worked closely with foundries and OSATs (outsourced assembly and test houses) to develop new processes and implement materials to address their unique requirements. This session will look at the dynamics of this increasingly complex part of the semiconductor supply chain.
Speakers:
Nick Yu
VP of Technology Development
Qualcomm
Nick Yu is a Vice President of Engineering at Qualcomm’s CDMA Technologies Division. He is currently responsible for setting Qualcomm’s semiconductor technology roadmaps including wafer fab process node, backend interconnect and packaging technologies. He manages engineering teams that are involved with our supply chain partners on execution of the technology roadmaps for Qualcomm’s chipset products. Nick has 18 years of experience with Qualcomm on low power wireless chipset and SoC development, including managing chipset design, advanced semiconductor technology, deep submicron circuit design and methodology development, advanced semiconductor R&D and packaging development. He is one of the architects of, and has participated in the definition and development of, many Qualcomm chipset products. Nick has an MSEE degree from Georgia Institute of Technology
Bridging the Fabless-Foundry Gap
BJ Woo
Senior Director Graphic/ PLD/CPU Business Development Division
TSMC
Fabless design houses and foundry need to collaborate closely to deliver successful product and to prosper together. This talk will specify the requirements and challenges for designers as the complexity of technology grows in advanced technology. Solutions to address those challenges are also provided to show how fables companies and foundry can collaborate and succeed.
For fabless design houses, major concerns include competitive technology selection with best performance/watt/cost, 1st Si success to enable fast time to market and stable/reliable supply support with decent yield and ample capacity to secure market segment share. Foundry will provide multiple process options with customization to address the unique requirements for different product applications. Meanwhile, accurate SPICE model, DFM (design for manufacturing), and IP validation will help improve 1st Si success rate and time to market.
In addition, stable/ reliable supply is one of the keys for fabless company to gain and secure market segment share. As such, Foundry needs to provide a more sophisticated manufacturing infrastructure to go after the best manufacturing excellence. Such infrastructure includes fully automated manufacturing system, Giga Fab for large scale of economy, speedy productization-from tapeout to volume production, steep yield learning curve, nano-scale precision control for uncompromised yield while technology scaling, product grade enhancement, and integrated service for mask, wafer, and backend for coherent quality and delivery.
In summary, bridging the gap between fabless design houses and foundry is the essential factor of the winning strategy. Both parties need to collaborate closely in design, technology and manufacturing areas. As a result, a successful product with best performance/watt/cost can be delivered to compete and to win in the market place. In addition, sufficient and reliable capacity support with manufacturing excellence, customer will not only win the business and will grow the business with high market segment share and profits.
BJ joined TSMC as Senior Director of Technology Roadmap Division in April 2009. She is currently in charge of the High Performance Technology definition for Graphics, PLD, CPU and Game Console Business Development Division.
Prior to joining TSMC, BJ has spent most of her career life in Intel Corp for 24+ years. Because of her excellent work and leadership, she was nominated by Intel and was honored as 2006 Hall of Fame for WITI (women-in-technology-international).
Supply Chain Realities, Challenges & Opportunities For Fabless
and Fablite Companies
Mike Noonen
Senior VP, Worldwide Sales & Marketing
GLOBALFOUNDRIES
Our industry has always had the cyclic reality of the semiconductor cycle to deal with. This challenge has been compounded by several factors in recent years that fabless and fab-lite companies must contend with. These are:
• Financial markets demanding higher returns and hence more operational efficiency
• Fewer options for leading edge manufacturing
• Product lifecycles that much shorter than design and even production times in some markets
• Disaggregated worldwide supply chain that can be disrupted by natural disasters
Mr. Noonen will outline these challenges and propose proactive ways to address them. He will give examples of how GLOBALFOUNDRIES and its partners are offering solutions mitigate risk and continue profitable semiconductor innovation.
Michael Noonen is Senior Vice President, Worldwide Sales and Marketing, for GLOBALFOUNDRIES. In this role, he is responsible for global customer relationships as well as all sales, marketing, customer engineering and quality functions. Noonen joined GLOBALFOUNDRIES in January 2012 with over 25 years of high technology product management, sales and marketing experience. Most recently he served as executive vice president, sales and marketing, with NXP Semiconductors from 2008 to 2011. Along with NXP’s CTO, he crafted and implemented NXP’s High Performance Mixed-Signal Strategy that resulted in 11 consecutive quarters of growth, a $5 billion business and NXP’s successful IPO in 2010.
Previous to NXP, Mike Noonen held several leadership positions with National Semiconductor, including vice president of the company’s Interface, Networking and Computing Businesses from 2001 to 2005 and senior vice president of Worldwide Sales and Marketing from 2005 to 2008, which were the most profitable years in the company’s history. Before joining National Semiconductor, he also worked for Cisco, 8x8, and NCR Microelectronics.
Noonen holds a Bachelor of Science degree in electrical engineering and holds multiple patents in the areas of internet telephony and video communications.
28nm Case Study: Successful Fabless & Foundry Collaboration
Xin Wu
Senior Director, Silicon Technology
Xilinx, Inc.
This talk will describe Xilinx’s strategy for riding the leading edge of each new process node and the importance of close collaboration with the supply chain, coupled with rapid short-loop learning, in enabling Xilinx to offer key technological innovations. Mr. Wu will highlight critical success factors for fabless-foundry collaboration with a case study of the world’s first 28nm FPGAs.
Xin joined Xilinx in 1993 as a new college graduate, serving as a key member of the silicon technology team over more than 10 process generations, starting with 0.6um. Currently, he is responsible for silicon technology, Stacked Silicon Interconnect (SSI) 2.5D/3D technology, and advanced package technology-design areas. Xin graduated from Peking University and UC Berkeley with M.Sc and PhD, respectively.
2:15PM - 3:45PM
Session #4: Advanced Packaging and Progress in 3D Integration
While 3D integration continues to offer the promise of packing ever-higher amounts of functionality into a smaller area, significant progress continues to be made in traditional packaging (such as package-on-package and wafer level packaging).
Speakers:
David McCann
Senior Director, Technical Business Operations
Global Foundries
The evolution toward silicon-based interconnect and packaging is having profound impact on how we think about technology development and the supply chain. Previously, companies in incremental steps of the supply chain could develop products relatively independently. Now they must work together to create solutions, or fail their common customers. Although the shortest path to market may be for the Foundry to do everything in-house, the path to the best solutions that will enable competitive costs and high volume adaption will be flexible supply chains with collaborative partnering, flexibility, and transparency.
David McCann is Sr Director for Packaging R+D at GLOBALFOUNDRIES in Malta, New York. In this role, Dave is responsible for Packaging R+D and back-end strategy and implementation. David started at GLOBALFOUNDRIES in 2011.
Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, most recently leading the BGA, Flip Chip and MEMS product groups. He was responsible for extensions of package technology, bump, applications, and business performance. Prior to this, Dave was responsible for the fcBGA and fcCSP business group at Amkor. He led cross-functional teams in various areas including networking product strategy, mobile product development, large die/lead free flip chip development, and wafer level product strategy. David worked closely with Amkor factories in Asia.
Prior to Amkor, David worked at Biotronik, GmbH in Portland, OR. Biotronik is a developer and manufacturer of implanted medical devices including defibrillators and pacemakers. David worked at Biotronik for 9 years and had various roles in Production, Process Engineering, Product Engineering, and Flip Chip implementation. His last role at Biotronik was leading the assembly, interconnect, and product transition from wire bond to flip chip.
David has supported the Electronic Component and Technology Conference for more than 10 years. This year he is Conference General Chair.
Ron Huemoeller
Senior Vice President
3D Amkor
This presentation will discuss some of the challenges and opportunities for high density 3DIC Through Silicon Via (TSV) product technologies in the semiconductor industry. TSV product technology offers significant opportunity in the advanced product sector of the semiconductor industry as compared to traditional System on Chip (SOC) methods for packaging die. The first part of this presentation will focus on the opportunities provided by TSV product technology in the following key areas: performance and power improvement, form factor reduction and in cost reduction at the system level. The second part of this presentation will focus on the challenges remaining in bringing this new product technology to high volume production as well as anticipated product launch dates. Particular focus will be given to the issues surrounding supply chain constraint as well as the issues associated with current state of the art approaches to completing the die stacking of these complex package structures.
Ron is currently Sr. Vice President of Adv. 3D Interconnect Platform Development at Amkor Technology. Prior to Amkor, Ron was Director of Engineering at Cray Computer Corporation in Colorado Springs, developing motherboards for state of the art Super Computers. He has been granted 58 U.S. patents. Ron holds a BS in Chemistry from Augsburg College with highest honors, a MBA from Arizona State University and a Master’s in Technology Management from the University of Phoenix
The Evolution of 3D ICs:
Leaping Ahead of Moore’s Law to Deliver a 6.8B Transistor Device
Sandeep Bharathi
Vice President of Engineering
Xilinx
This talk will focus on the evolution 3D ICs, comparative approaches by industry pioneers, and a 28nm 3D case study of the world’s highest capacity FPGA, built using Xilinx’s revolutionary stacked silicon interconnect (SSI) technology. The case study will cover technology, applications and power benefits. It will conclude with a 3D standards call to action for our industry.
Sandeep Bharathi is vice president of engineering with responsibility for FPGA digital design development, CAD and FPGA product tape outs. Bharathi joined Xilinx in 2010, bringing more than 20 years experience in engineering and management positions with semiconductor companies. Prior to Xilinx, he spent seven years at Advanced Micro Devices, where he led all aspects of CPU design in multiple process technology nodes, including 32nm server and desktop CPU development. Before that, Bharathi held several engineering and management positions at Mobilian Corp. (acquired by Intel Corp.). Previously, he served in engineering positions on CPU design and development teams at Intel Corp.
Bharathi earned a BSEE from Bangalore University, India and MSEE from New Jersey Institute of Technology. He holds one patent in ‘zero detect circuit and method for high frequency integrated circuits’.
Innovation & Collaboration in the 3D TSV Integration Ecosystem
William Chen
ASE Fellow Sr. Technical Adviser
ASE Inc.
The global market for smart phones, cloud computing, and ubiquitous electronic devices, is accelerating demand for increased bandwidth, high performance, and super intelligence in electronic products. The concept of TSV and 3D stacking has given rise to waves of technology innovation towards heterogeneous integration. How will emerging innovation be implemented and brought to the market place? This presentation will review the intersecting landscape of technology and business innovation, and discuss how our ecosystem will collaborate to meet the promise of More Moore and More than Moore.
Bonus: Executive Roundtable
Manufacturing engineers are increasingly being challenged to manage ongoing problems associated with the availability of parts and long lead times for near obsolete and fully obsolete fabrication equipment. This meeting will focus on innovations in equipment, materials, and processes are an important part of any continuous improvement effort for an optimum and improved product cycle time.
Moderator:
Sanjay Rajguru
Director
Sematech Manufacturing Initiative
Participants:
Ashish Bhatnager
Managing Director, Engineering Head
SPG Applied Global Services
Joerg Recklies
Infineon
MIke Barrow
Executive VP & COO
International Rectifier
Wednesday, June 6th
9:00AM - 10:30AM
Session #5: Maximizing the Longevity of Investments
Plenty of semiconductor devices are still produced on 200mm wafers at larger geometries, including MEMS, power electronics, analog devices, wireless chips and others. What is the best solution to maximizing the longevity of 200mm? When would it make sense to move to 300mm equipment? Presenters will discuss strategic plans that include technology, product development, competitive analysis and capital investments..
Strategic Planning in a Changing World
Mike Barrow
EVP and COO
International Rectifier
The global rate of change has never been greater and strategic business planning is more critical now than ever before. The typical strategic plan includes market analysis, technology roadmaps, product development, and capital investments, etc. We may also focus to costs, regulations, innovation, product quality, tax rates, lending rates, along with other business risks. Predicting the future has never been an easy task and usually involves a linear extrapolation of historical trends, but disruptive events can have a major impact on the financial health and survival of a business. There are new risks that need to be considered and this presentation will focus on factors not often considered in the typical planning process.
Michael Barrow is the EVP and Chief Operations Officer at International Rectifier since April 2008 and he is responsible for developing a world-class Technology Development and Manufacturing Operation utilizing both internal and external factory resources.
He has 35 years of computing, semiconductor and operational leadership experience with International Rectifier, Amkor Technology, Intel and Unisys/Burroughs. At Amkor Mike served as Senior Vice President and General Manager of the Flip Chip and Wafer Level Business Unit leader where he was responsible for the strategic direction/business growth and P&L for the business unit. Prior to Amkor Mike spent 12 years at Intel, as the Technology General Manager of Intel’s Communications Group and Technology Manager of Intel’s Chip Set Group. Before joining Intel, Mike spent 15 years at Unisys and held positions in increasing levels of responsibility having begun his career as a power design engineer at Electro Pacific Inc. designing switching power supplies and motor generators.
Mike holds a BSEE/BSME degree from Natal Technikon (Institute of Technology), Durban, South Africa and holds 22 United States Patents and Invention Awards.
Gary Robertson
Division General Manager
KLA-Tencor
Gary Robertson has been at KLA-Tencor in Milpitas, California, since 2005 and is Division General Manager of K-T Certified (KTC). KTC is the K-T Services group responsible for system refurbishment, re-certifications and upgrades. Prior to joining K-T, Gary worked at Applied Materials in a variety of posts including running the Refurbishment Division.
Tool Obsolescence and the Impact on 200mm Manufacturing
Sanjay Rajguru
Director
ISMI
Moore’s law dictates that some portion of our product base becomes obsolete every year. This means that a growing list of 200mm manufacturing parts, also become obsolete every year. Tool obsolescence is possibly, the most critical problem faced by legacy manufacturers. ISMI will present our findings, compiled from over one year’s research, including the root cause and possible solutions, both tactical and strategic, for dealing with tool obsolescence.
Sanjay Rajguru is the director of International SEMATECH Manufacturing Initiative (ISMI). In this position he is responsible for the consortium’s manufacturing technology programs, including the Manufacturing Capabilities and Mature Fabs programs, which are focused on the systematic improvement of manufacturability, including factory and equipment stability, productivity and cost improvements, and equip-ment lifecycle management. In addition, he is responsible for overseeing the ISMI ESH Technology Center, the industry’s first world-wide collaborative research organization including chip manufacturers and equipment and material suppliers devoted to collectively finding and implementing the most cost-effective, environmentally friendly manufacturing processes and procedures.
Prior to joining ISMI, Rajguru was a fab manager at National Semiconductor for 13 years and has also held engineering and management positions with Nortel Semiconductors, including director of operations for the optoelectronics division, fab manager for silicon, GaAs and SAW devices, process engineering manager and lithography process engineer.
Increasing ROI on Capital Projects through Effective Application of Site & Financial Incentives
John Frank
Senior VP Industrial and Advanced Technology
CH2MHill
Innovative project delivery and economic impact analysis methods provide opportunities to reduce infrastructure costs in both new and existing high-tech facilities. Reduction of capital and operational costs can be enhanced through careful consideration of such issues as incentive collaboration, leveraging existing infrastructure, high-tech leading job multipliers, and manufacturing impact analysis.
This new model, which aligns with the business goals, community profile, and core intellectual property of a target region, helps optimize value on high tech capital intensive projects. When properly applied, these approaches combine to achieve strong return on investment, thereby justifying the incentives. The impact of these approaches varies for different technical industries (e.g. semiconductor facilities, flat panel manufacturing and new photovoltaic high-volume manufacturing sites). Collaboration between business and government is critical, coupled with careful attention to a region’s attributes and assets as a basis of negotiation, to maximize the capital and project delivery potential of the technical project.
In close coordination with governmental stakeholders, the model integrates all of the following into a single point of responsibility:
• Feasibility analysis
• Investment planning
• Valuation chartering
• Facility design and construction
• Facility operations
Demonstrated results are accelerated schedules, capital optimization, cost reductions and reduced contractual risks, culminating in increased acceptance of this project delivery approach.
John joined CH2M HILL in 2007 with 25 years experience of business management, design, construction, major Semiconductor operations and engineering management. He has been involved globally in many challenging and leading edge technology projects including multiple site selection programs, financial analysis, site and community developments, incentive package creation, client executive sponsorship, photovoltaic, renewable energy, flat panel, 300 and 450mm semiconductor and nanotechnology projects.
Prior to becoming part of the CH2M HILL team, John was responsible for Electronics Business Unit of M+W Zander, Hitachi Semiconductor (America) Inc. (Irving, TX) and Zilog Corporation’s (Nampa, ID) Construction, Facilities and Semiconductor Operations as the Vice President of Operations.
John also worked for 5 years with SEMATECH where his team was recognized for achieving the first 200mm 250 nanometer devices. His other roles included 250 to 130 nanometer lithography strategy for manufacturing implementation, Patent Review Board Committee Member, Chairman for SPIE Micro Lithography Conference and Technical Advisory Board Member for Wisconsin, Stanford and Berkeley Universities.
John graduated with BS, Chemical Engineering from the State University of New York at Buffalo. Currently John has co-authored multiple patents and has been published SPIE, Solid State Technology, Semiconductor Technology, Electronic Business News, Cleanrooms Magazine, Constructioneer and Micro Contamination in addition to multiple news agencies.
