2010 Conference Program

Conference Program

The ConFab
Loews Lake Las Vegas Resort
Las Vegas, Nevada
May 16-19, 2010

Monday, May 17, 8:00-8:45AM

Keynote:

What's Driving Semiconductor Consumption

Eli Harari
Founder, Chairman and Chief Executive Officer
SanDisk Corporation

Eli Harari has served as CEO of SanDisk since the company’s founding in 1988, and has built SanDisk into the global leader in flash memory cards, with revenues of $3.57 billion in 2009. A pioneering leader in both technology and business, Harari holds more than 100 U.S. and international patents in non-volatile semiconductor devices. Under Harari, SanDisk has grown into a major international retail brand, serving customers through more than 240,000 retail storefronts worldwide.

From 1973 to 1983, Harari held research and management positions with Hughes Microelectronics Ltd., Honeywell Inc. and Intel Corporation. In 1983, he founded Waferscale Integration Inc., serving as the company’s president and chief executive officer until 1986 and as chairman and chief technical officer until 1988.

Along with SanDisk co-founders Sanjay Mehrotra and Jack Yuan, Harari received the 2006 Reynold B. Johnson Data Storage Device Technology Award from the Institute of Electrical and Electronics Engineers (IEEE). In 2008 he received the Global Semiconductor Alliance’s Dr. Morris Chang Exemplary Leadership Award, and in 2009 he received the IEEE Robert N. Noyce Medal recognizing his “leadership in the development and commercialization of flash memory technology.”

Harari holds a Ph.D. in solid state sciences from Princeton University and a B.S. in physics with honors from Manchester University.

Session 1

Monday, May 17, 8:45 – 11:00 AM

Economic Outlook for the Post-Recession
Semiconductor Industry

As the world has worked its’ way out of the worst economic downturn in over 60 years, our industry and most companies had to significantly adapt their businesses to weather the unprecedented recession. As we continue to emerge from this worst ever down-cycle, companies face a variety of issues such as changing customer bases, shrinking supplier bases, less capital availability, and higher R&D costs to name a few. The question is how do different businesses plan in the new environment?

The session will begin with a general economic overview with regional forecasts and different industrial outlooks to be provided. We will then hear from a number of vantage points within our industry. Companies within the electronics food chain see their businesses through different lenses. Our cross section of experts assembled will provide their perspectives on the impact of the downturn, how it affected their 2010/11 plans and how they see the “new normal” from their industry vantage points.

Session Leader:

David Bennett
VP of Alliance
Global Foundries

David Bennett is the Vice President of Alliances for GLOBALFOUNDRIES with global responsibility in this role for the corporation. Prior to this David held several executive management positions at AMD during a 16-year tenure. Prior to joining AMD, Bennett worked at SEMATECH leading the Technology Transfer function as a Texas Instruments (TI) assignee. Prior to that, he was a Process Control Manager at TI with responsibility over two wafer manufacturing fabs in Dallas. David started his career in the semiconductor industry with TI in 1984. He obtained BS and MS degrees in Chemical Engineering from the Colorado School of Mines in 1982 and 1984 respectively. David is a 25 year veteran of the semiconductor industry and has published a variety of papers in the area of technology management and technology transfer. He has served on the Board of Directors at SEMATECH as well as several other companies/organizations.

Speakers:

Bruce McDougall

CFO

Global Foundries

Bruce McDougall is the Chief Financial Officer (CFO) of GLOBALFOUNDRIES. As CFO, he is responsible for overall financial management of the company and its financial reporting and transparency. Prior to joining GLOBALFOUNDRIES, McDougall was with Mubadala Development Company, where he was seconded as CFO to EMAL International, a US$5.7 billion joint venture greenfield aluminium smelter and power plant project under construction in the UAE in partnership with the Mubadala Development Company. In this role he was responsible for arranging financing, negotiating key project agreements, and implementing operations, finance, treasury, risk management and business planning support functions.

McDougall’s professional experience also includes management positions in operations and business services at Curragh Mines (Wesfarmers) and Rio Tinto.

McDougall was a member of the board for Guinea Alumina Corporation and was a member of the board for the Rio Tinto Staff Superannuation Fund from 2001 to 2002. McDougall is a CPA, holding Bachelor of Business degree.

David Reed
Vice President
Texas Instruments

Mr. David W. Reed is Vice President of Texas Instruments Inc., and is responsible for the company’s Global Quality, Customer Quality Engineering, and Packaging Groups which includes both internal/external manufacturing and business operations. Mr. Reed is in the Technology & Manufacturing Group (TMG) and his last two assignments since 2001 were as the manager of TI’s Global Operations for Assembly/Test/Package Operations and Sub-Micron Logic Fabs Operations.

During his 25-year career with the company, Mr. Reed has managed and worked in manufacturing, operations, R&D, and business units across the breadth of TI’s semiconductor operations. A 1981 graduate of Austin College (BA Chemistry) and 1983 graduate of Texas A&M (BS Chem. Engr.), Mr. Reed began his TI career in 1984 with the Standard Linear Logic (SLL) Operations and Business. Mr. Reed’s various company assignments required 3 Ex-Pat postings for Global operations, fab start-ups, production ramps, and Joint Ventures (JV). David’s program management experience covers 0.35um Logic Node Development, 16M/64M/256M DRAM Development & JV Start Ups, integration of Microelectronics Manufacturing Science & Technology (MMST DARPA/TI 1993 world record 3 day 100% RTP cycle time), 180nm/150nm copper based Logic Node Development & Ramp, Digital Light Projection (DLP tm), Automotive 0 ppm, Global Packaging Operations, and Global Test Operations.

Mr. Reed has lived in Germany, Philippines, Italy, USA, Singapore, and Japan for 20 locations worldwide and earned an MBA in Corporate Finance from University of Dallas (1990).

Aart DeGeus
Chairman and CEO
Synopsys, Inc.

Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA).

With 25 published papers and numerous industry honors, Aart has long been considered one of the world's leading experts on logic simulation and logic synthesis.

Among the prestigious technology awards that Dr. de Geus has received is the honor of being named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was honored for pioneering the commercial logic synthesis market with the IEEE Circuits and Systems Society Industrial Pioneer Award in 2001, as well as for his “contributions to, and leadership in, the technology and business development of Electronic Design Automation” with the 2007 IEEE Robert N. Noyce Medal.

He has been singled out as an innovative business leader as well. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine. In November 2005, Electronic Business magazine selected Dr. de Geus as one of “The 10 Most Influential Executives.” In November of 2007, he was awarded the Silicon Valley Leadership Group (SVLG) “Spirit of the Valley” Lifetime Achievement Award. In October 2008, he was presented with the Phil Kaufman Award for distinguished contributions to EDA. And in December, 2009, he was awarded the GSA “Morris Chang Exemplary Leadership Award.”

Dr. de Geus is active in the business community as Chairman of the Board of the Silicon Valley Leadership Group (SVLG), a member of the board of Applied Materials, and a member of TechNet, the Global Semiconductor Alliance (GSA), and the Electronic Design Automation Consortium (EDAC).

Dr. de Geus is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.

Duncan Meldrum
Chief Economist
Air Products, Inc.

Duncan Meldrum is the Chief Economist for Air Products and Chemicals, Inc., a $5.5 billion industrial gas and chemicals company serving customers in over 30 countries. As Chief Economist, he assesses the impact of the economic environment on the company’s performance for the executive management team and develops global economic assumptions for the company’s operating plans. He provides operating groups with pricing assistance, contract support and market analyses. He also serves as the company’s economics spokesperson.

He received a B.S. degree from the U.S. Naval Academy in 1973, a M.S. degree in Operations Research from the U.S. Naval Postgraduate School in 1974, and a Ph.D. in Economics from Lehigh University in 1992. He is a member of the Advisory Committee to the U.S. Census Bureau. He serves as a director on the boards of the APCI Federal Credit Union and the nonprofit Parkette National Gymnastics Center. He is a past president of the National Association for Business Economics. His other professional associations include the Conference of Business Economists, the National Business Economic Issues Council, and the American Economics Association.

Bill McClean
President
IC Insights, Inc.

Mr. McClean began his market research career in the integrated circuit industry in 1980 and founded IC Insights in 1997. During his 29 years of tracking the IC industry, Mr. McClean has specialized in market and technology trend forecasting and was responsible for developing the IC industry cycle model. At IC Insights, he serves as managing editor of the company’s market research studies and reports. In addition, he instructs for IC Insights’ seminars and has been a guest speaker at many important annual conferences held worldwide (e.g., SEMI’s ISS and Electronic Materials Conferences, The China Electronics Conference, and The European Microelectronics Summit). Mr. McClean received his Bachelor of Science degree in Marketing and an Associate degree in Aviation from the University of Illinois.

Session 2

Monday, May 17, 1:45 PM- 3:15 PM

New Dynamics of the Semiconductor
Industry's Infrastructure

In the past two decades, disintegration of design and process has fostered the rapid growth of Fabless companies and wafer foundries in semiconductor industry. Such a trend has made IDM’s becoming endangered species. As we continue on Moore’s law to 20nm and wafer size to 450mm, new challenges arise in design/process interactions and in cost sharing on R&D and volume production. Can the fabless/foundry business model continue to prosper? Or would we see new changes or inflection in semiconductor infrastructure? This session brings experts from both fabless and foundry sides and from IDM to address the future dynamics in our industry and discusses new opportunities and challenges ahead of us.

Session Leader:

John Chen
VP of Technology and Foundry Operations
Nvidia

Dr. Chen has 30 years of experience in IC industry ranging from IDM to Foundry to Fabless companies. He started his career as a researcher in Hughes Research Laboratories, subsequently at Xerox Palo Alto Research Center (PARC). Most of his work involves CMOS devices and process technologies. Later, he has had various technical and managerial positions in technology development and IC manufacturing. He was the Director of Technology Development at Cypress Semiconductor.

In 1992, He joined TSMC as the Senior Director responsible for Product Engineering and Backend Operations. He was later promoted to the V.P. of R&D, building technology base for TSMC, defining and driving technology roadmaps for the foundry industry. In 1997, he joined the start-up team as the V.P. of Operations for WaferTech, a JV then led by TSMC in Camas Washington. He built and ramped up the fab to 30 thousand wafers a month. During his last year in WaferTech, he became the V.P. of Business Development. In 2004, he joined NVIDIA as the V.P. of Technology and Foundry Operations.

Dr. Chen has published 100 papers, mostly by IEEE. His book on " CMOS Devices and Technology for VLSI ", was published by Prentice Hall in 1990. He was elected as an IEEE Fellow in 1992 for "leadership in and contributions to advanced CMOS device and process technology". He was a member of the Technical Advisory Committee for ITRI, Taiwan from 1988 to 1992. He now serves on the technical committees of SIA and GSA.

Dr. Chen was a Howard Hughes Doctor Fellow and received a Ph.D. in EE and an Executive Management degree, both from UCLA. He also holds a M.S. from University of Maine and a B.S. from National Taiwan University, both in E.E.

Speakers:

Jim Clifford

Senior Vice President & General Manager of Operations

Qualcomm CDMA Technologies

Jim Clifford is currently Senior Vice President and General Manager of Operations at QUALCOMM CDMA Technologies (QCT). In this role, Clifford is responsible for IC and Packaging Technologies, Procurement, Integrated Supply and Demand Planning, and Quality in addition to managing the overall operations functions for the QCT division.

Clifford has been at QUALCOMM since 1994, when he joined the company as a director of business development and oversaw product development in its OmniTRACS division. In 1996 he moved to QCT as director ASICs, and has focused on sourcing IC chips during the explosive growth for CDMA technology. He was promoted to vice president of operations in 1997, senior vice president in 2000, and GM of Operations in 2003. Prior to his career at QUALCOMM, Clifford had more than 20 years of experience at Unisys in positions ranging from IC design to vice president and general manager of mainframe computer manufacturing.

Clifford holds a Bachelor’s of Science in Physics from San Diego State University, and is a graduate of the Executive Program for Scientists and Engineers program offered by the University of California, San Diego.

John Lin,

Director of Mfg Technology Center

TSMC

John Lin received his PH. D. degree in Opto-Electronic Engineering from University of Oxford in 1994.

He has worked on semiconductor technology development in Industrial Technology Research Institute, Taiwan and then in Vanguard International Semiconductor Corporation from 1994 to 1998.

He joined Taiwan Semiconductor Manufacturing Company as a department manager of mask technology on Oct. 1998 and later in lithography technology development through 0.25um down to 45nm. Since Feb. 2006, He has been the Director of Manufacturing Technology Center.

He has given a few invited talks at "Immersion Lithography", and "450mm Wafer Strategy“, and issued 40 US patents, author or co-author of 25 technical papers. He also awarded to the National Excellent Young Engineer in 2004 and the National Outstanding Engineer in 2008 by the Chinese Institute of Engineers.

Peter Rickert

TI Fellow & Platform Director
Application Specific Products
Texas Instruments Inc.

Peter Rickert, P.E., is a TI Fellow and Senior Member of the IEEE. He is currently responsible for the Platform Technology Development for the Application Specific Products and Wireless organizations at TI. This means he manages the cross-functional team which encompasses the definition, development, & deployment of TI's newest process technologies, including the 65nm, the 45/40nm, and the 28nm platforms.

In 2000, Rickert was elected a TI Fellow in recognition of his leadership of new technology introductions and ramp to production. He has held multiple engineering & management roles across TI during his 28 year career, including assignments in Houston, in France, and now Dallas.

He is widely recognized for his broad technical leadership & knowledge in ASIC design, process technology, test, & program management.

Rickert received his Bachelor of Science degree in EE at Clarkson University in 1980. He became a Registered Professional Engineer in the state of Texas in 1992 and is a Senior Member of the IEEE.

Hans Stork

Chief Technology Officer & Group VP
Applied Materials Inc.

Dr. Hans Stork was named chief technology officer and group vice president for the Silicon Systems Group at Applied Materials in October 2007, where he is responsible for leading the company’s roadmap for silicon technology equipment. In this role, Dr. Stork oversees integrated technology development across the silicon products, coordinates the organization’s industry and university engagements and ensures value to customers by leveraging understanding of technology interactions to optimize differentiated product solutions.

Prior to joining Applied Materials, Dr. Stork served as CTO and senior vice president of Silicon Technology Development for Texas Instruments from 2001 to 2007. He served as lab director for ULSI and Storage & Systems Labs for Hewlett Packard from 1994 to 2001, and was senior manager for Exploratory Si Technology at IBM from 1982 to 1994, where he received two outstanding achievement awards.

Dr. Stork is an IEEE Fellow and member of the board of directors for Semiconductor Research Corporation and the Semiconductor Industry Association technology strategy committee. He previously served as a member of the advisory committee for the Texas State Emerging Technology Fund from 2005 to 2006 and was a member of the board of directors for Sematech from 2002 to 2007.

Dr. Stork earned both a bachelor of science and Diplom-Ingenieur degree in electrical engineering from Delft University of Technology, The Netherlands. He earned his doctorate in electrical engineering from Stanford University.

Tuesday, May 18, 8:00 AM - 8:45 AM

KEYNOTE: Electronics in Automotive Applications

Keynote Presenter:

Mr. Norimasa Kishi, Ph.D
Research Director
Nissan Research Center
Nissan Motor Co., LTD

Mr. Kishi joined the central Lab. of Nissan Motor Co. in '1978 and has been responding to Research and Development of intelligence of Car Electronics. Car Navigation, Voice Control System. Major Awards: Science and Technology Agency (Voice Recognition and Control System); Society of Automotive Engineers of Japan (Bird view Navigation System); The Japanese Society for Artificial Intelligence (Driving Position System,)

Session 3

Tuesday, May 18, 8:45 AM - 10:15 AM

Next Generation Lithography

Lithography- Can't We All Just Get Along?

Everybody loves a good fight and lithographers of the past decade have been no exception, with the most vocal expressing their opinions on which single lithography technology will reign as champion. Behind the headlines, lithographers have always worked to extend existing technologies which reuse the expensive capital base while in parallel inserting new technologies as they become manufacturable to enable smaller features. A new wave of lithography agnostics (or perhaps pragmatists), mostly users, is becoming more vocal in professing that “whatever works” will be used to continue the evolution of lithography. This presents technical challenges in extending existing technologies, compatibility requirements for novel technologies to work in a mix-and-match mode, and potential market size challenges as adoption rates for new technologies may vary by segment.

A panel of experts representing device manufacturer lithography developers, mask makers, R&D consortia, and equipment suppliers will share perspectives on this topic.

Session Leader:

Janice Golda

Director, Lithography Capital Equipment Development

Intel

Janice manages an organization responsible for creating strategies and working with Intel’s lithography, mask, and metrology suppliers and sub-suppliers to deliver equipment meeting Intel’s roadmap technology, capacity, and cost requirements. She has represented Intel on the SEMATECH Lithography Program Advisory Group, the US Lithography Technical Working Group, and the International EUV Symposium, and has presented and published for numerous industry forums. Janice is a member of the Berkeley CXRO Advisory committee and is Chairman of the Board for the EUV LLC. She holds one US patent. Janice joined Intel in 1989 and has held positions in lithography process engineering and program management. Janice earned a BS degree in Electrical Engineering from Cornell University.

Speakers:

Peter Jenkins
VP of Marketing
ASML

Peter Jenkins joined ASML in 1991 where he has held various product and commercial management positions including international assignments to South Korea in 1996 and Hong Kong in 1999. Mr. Jenkins returned to The Netherlands as Vice President of Marketing in 2005.

Prior to joining ASML, Mr. Jenkins gained extensive experience in Lithography and Semiconductor processing at LSI Logic and Plessey Research in the United Kingdom. Peter studied BSc Economics at Bath University, England.

Naoya Hayashi
Research Fellow
Dai Nippon Printing

Naoya Hayashi received his BS degree in applied chemistry, and MS degree in electric chemistry from Tokyo Institute of Technology, Tokyo, Japan. He joined Dai Nippon Printing Co.,Ltd (DNP) in 1977.
He has been responsible for development of photomask technologies, such as electron beam exposure systems, resist materials and processes, phase-shifting materials, and NGL masks for EUV and Nanoimprint, for more than 30 years at DNP. He is the first and the only Research Fellow of DNP since 2007.

Harry Levinson
Sr. Fellow & Manager Strategic Lithography Technology
GLOBALFOUNDRIES

Harry J. Levinson is a Sr. Fellow and manager of GLOBALFOUNDRIES’s Strategic Lithography Technology Department, which is responsible for advanced lithographic processes and equipment. Dr. Levinson started his career in Bipolar Memory Development at AMD, then spent some time at Sierra Semiconductor and IBM, before returning to AMD – now GLOBALFOUNDRIES – in 1994. During the course of his career, Dr. Levinson has applied lithography to many different technologies, including bipolar memories, 64Mb and 256Mb DRAM development, the manufacturing of applications-specific integrated circuits, thin film heads for magnetic recording, flash memories and advanced logic. He was one of the first users of 5´ steppers in Silicon Valley and was an early participant in 248 nm and 193 nm lithography.

Dr. Levinson also served for several years as the chairman of the USA Lithography Technology Working Group that participates in the generation of the lithography chapter of the International Technology Roadmap for Semiconductors. He has published numerous articles on lithographic science, on topics ranging from thin film optical effects and metrics for imaging, to overlay and process control, and he is the author of two books, Lithography Process Control and Principles of Lithography. He holds over 40 US patents. Dr. Levinson is an SPIE Fellow and chairs the SPIE Publications Committee. He has a BS in engineering from Cornell University and a PhD in Physics from the University of Pennsylvania.

Tatsuhiko Higashiki
Senior Manager
Process & Manufacturing Engineering Center
Toshiba Semiconductor Company

Tatsuhiko Higashiki is the senior manager of all lithography and mask process department in TOSHIBA Research and Development Center. He started working on the developing exposure tools in 1985. Moreover, he has been developed the scanner technologies, such as exposure tool management and strategy making, alignment and overly technologies, aberration monitor and simulation technologies, OPC and lithography design, and APC technologies. His current research interests are advanced lithography such as EUV lithography. He received his Doctor’s of Engineering (1994) from the National University of National Electro-Communications.

Session 4

Tuesday, May 18, 2:15 PM - 3:45 PM

Panel Session: Semiconductor Manufacturing R & D:
Working Together to Minimize Costs

R&D costs are escalating due to a demand for continued shrinks, more advanced device structures and even a move to 450 mm wafers. At the same time, a massive restructuring is underway that will leave only a handful of companies producing devices at the leading edge. This panel session will examine successful collaborative efforts that can help address the R&D funding challenge.

Session Leader:

Pete Singer
Editor
Solid State Technology

Peter Singer has been covering the semiconductor and related industries for more than 26 years. Now Editor-in-Chief of Small Times and Solid State Technology, he was previously with Semiconductor International. He has authored more than 200 articles on all aspects of semiconductor manufacturing and related industries, including optoelectronics, photonics and photovoltaics. He has a degree in electrical engineering from the University of Illinois, Champaign-Urbana.

Dan Armbrust
President & CEO
Sematech

Daniel Armbrust was named President and Chief Executive Officer of SEMATECH in November, 2009, with the responsibility to lead the consortium’s advanced technology R&D programs in lithography, front end processes, interconnect, and metrology, and oversee SEMATECH’s subsidiary, the International SEMATECH Manufacturing Initiative (ISMI).

Armbrust previously spent 25 years at IBM Corporation, culminating in his tenure as Vice President of 300mm Semiconductor Operations for the company’s Systems Technology Group where he was responsible for the operation of IBM’s 300mm fab in East Fishkill, New York, which develops leading edge technologies with IBM’s alliance partners and manufactures products for IBM and OEM customers. His leadership was marked by successful efforts to improve operating efficiency, lead executive collaborations within the industry, and build strong technical teams.

Prior to his role as Vice President, Armbrust served as Director of 300mm Engineering and Strategic Client Executive for IBM’s Systems and Technology Group. He began his career at IBM in 1983 and progressed through a variety of assignments in process development, manufacturing and client engagement.

Armbrust earned a bachelor’s degree in ceramic science and engineering from Pennsylvania State University as well as a master’s of science degree in manufacturing systems engineering from Rensselaer Polytechnic Institute.

Larry Sumney
President and CEO
Semiconductor Research Corp.

In 1982 Larry W. Sumney was selected by the Semiconductor Industry Association to head up the industry's new research consortium: the Semiconductor Research Corporation. He was named President and CEO in 1984, and a member of SRC Board of Directors several years later. In 1997 he became Chairman of the Board for MARCO, a wholly-owned subsidiary of SRC, which manages the Focus Center Research Program. In 2005 he became Chairman of the Board for NERC, another wholly-owned subsidiary of SRC, which manages the Nanoelectronics Research Initiative. Moreover, since the SRC Education Alliance was established, he has also held the position of Board Chairman. In 2007 SRC was awarded the National Medal of Technology, the same year that marked both the 25th anniversary of SRC and the 25th year of Mr. Sumney's leadership of the organization. Today, Mr. Sumney continues to lead SRC in its growing activities and expanding impact.

Mr. Sumney began his career in 1962 as a research physicist at the Naval Research Laboratory, later serving as Research Director of the Naval Electronics Systems Command where he defined broad basic research initiatives to support advanced systems needs. Following that assignment, Mr. Sumney was named the Director of the Tri-Service Charge Coupled Device (CCD) Technology Development Program by the Office of the Undersecretary of Defense. He next joined the Office of the Undersecretary of Defense Research and Engineering where he had overall responsibility for the creation, implementation and management of the Very High Speed Integrated Circuits (VHSIC) Program, the largest (~ $1B) technology development program in the Department of Defense. For this work he was named a "VHSIC Pioneer" in 1987.

Mr. Sumney received his B.A. from Washington and Jefferson College in 1962 with Honors in Physics. He earned his Master's in Engineering Administration (MEA) from George Washington University (GWU) and has completed his course work toward the DSc degree in Systems Engineering and Mathematics, also at GWU.

Subramanian Iyer
Distinquished Engineer at IBM Systems & Technology Group
IBM

Subramanian S. Iyer is Distinguished Engineer and Chief Technologist for the Semiconductor Research and Development Center, IBM Systems & Technology Group, and is responsible for setting semiconductor technology direction. Until recently he was Director of 45nm CMOS Development.

He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture silicon-on-insulator materials. He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor, the development of embedded DRAM technology, and the development of eFUSE technology.

His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap at 22nm and beyond. He holds over 40 patents and has received 19 Invention Plateau awards at IBM. He received the Distinguished Alumnus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 150 articles in technical journals and several book chapters and co-edited a book on bonded SOI .

He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. Dr. Iyer is a Fellow of IEEE and a Distinguished Lecturer of the IEEE. He obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles.

Lode Lauwers
Senior Business Development Director
IMEC

Lode Lauwers was born in St.-Joost-Ten-Node, Brussels, on November 14, 1962. He has a degree as Master in Electro-technical and Electronics Engineering (1985) and Ph. Doctor in the Applied Sciences (1993).

In January 2005, he joined IMEC, the nanoelectronics R&D Center in Leuven, Belgium, as Director Strategic Program Partnerships. In this role, he is responsible for business and partner interactions in IMEC’s core program in CMOS technology, in partnership with

leading IC companies worldwide; since 2009 he became sr. Business Director heading IMEC’s team of business development managers, with a responsibility for the IMEC business interactions in all R&D fields.

From 2000 to 2004, he was general manager of ASIC design house Easics NV, a wholly-owned subsidiary of TranSwitch Corporation, a provider of Application-Specific Standard Products for the telecom industry. From 1992 to 2000, he was sr. scientific advisor in IWT, institute for the promotion of Science and Technology in Flanders, where he coordinated and advised for government funding in local and European cooperative networks in micro-electronics and telecommunications.

From 1985 until 1992, he was researcher in IMEC, in the area of MOS device modelling and simulation, which was also the subject of his PhD in 1993.

Session 5:

Wednesday, May 19, 9:00 AM - 10:30 AM

The Economics of 3D IC

Through Silicon Vias (TSVs) have long been proposed as a natural progression from 2D to 3D interconnects with the promise of relatively low process complexity while delivering high performance, lower power consumption, high density and high functionality. However, with the continuous scaling of incumbent technologies, TSVs have largely stayed in the realm of universities and research organizations until recently. The industry currently faces the challenge of rapidly introducing several complex technology solutions to maintain the density and functionality roadmap. TSVs present a very attractive alternate solution. This session will examine the current state of TSV technology, with a view towards cost and infrastructure readiness for high volume manufacturing.

Session Leader:

Sitaram Akalgud
Director, 3D Interconnect Division
Sematech

While on assignment to SEMATECH from Qimonda/Infineon Technologies, Arkalgud directed SEMATECH’s Interconnect division for three years, during which time he led efforts to screen, characterize, and improve the performance of low-k dielectric materials for the ITRS 45 and 32nm technology generations, and also initiated the exploration of next-generation 3D interconnects. Working directly for SEMATECH in his new role, Arkalgud will lead an expanded 3D program that will drive the industry’s most comprehensive research into the potentials of 3D interconnects using through silicon vias. In exploring the different 3D options, including wafer-to-wafer and die-to-wafer integration, Arkalgud and his researchers will define and map 3D technology options, develop unit processes and metrology, and ultimately demonstrate 3D’s functionality and reliability.
“We are delighted that SEMATECH and our industry partners will continue to benefit from Sitaram’s expertise,” stated Dao. “Support and momentum are building for 3D, and Sitaram’s strong technical background, leadership, and collaborative skills are perfectly suited to building, promoting, and realizing this major SEMATECH 3D initiative.”

Prior to his assignment at SEMATECH, Arkalgud served as Infineon’s director of the MRAM Development Alliance between Infineon and IBM. Earlier, he worked as a Technology Officer for the Memory Products Division and product manager for Ferroelectric RAM development at Infineon. Arkalgud came to Infineon from Motorola Inc., after working for nine years in several advanced logic and memory projects.
The author of more than 26 publications and presentations, and holder of 14 U.S. patents, Arkalgud earned a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India.

Speakers:

Matt Nowak
Director of Engineering in VLSI Technology Group
Qualcomm

Matt Nowak is Director of Engineering in the VLSI Technology Group of Qualcomm’s CDMA Technology Division. His responsibilities include leadership of Advanced Semiconductor and Packaging Technology Initiatives such as thru silicon stacking, advanced memory technology, Design for 3D, spintronics, and “More than Moore” initiatives. He manages a combination of internal advanced development teams, supplier JDPs, and consortia and university projects.
Matt has over 30 years of semiconductor industry experience in a variety of technical, management, and business roles including wafer fab processes and devices, CMOS ASIC technology, compound semiconductor RF devices, package design and assembly, IC design tools and methodologies, technology transfer, foundry interfacing, and advanced technology. Prior to joining Qualcomm in 2004, Matt worked for the Semiconductor Development group of Unisys/Burroughs Corporation and for the Research Laboratory of Varian Associates. He holds BS and Masters degrees in electrical engineering from Cornell University and has carried out graduate studies at Stanford University and UC San Diego. Matt is a Senior Member of the IEEE and has numerous publications
and patent filings.

Mario A. Bolanos
Strategic Packaging Research & External Collaborations Manager
Texas Instruments

Mario Bolaños is an industry veteran with more than 30 years of experience in the semiconductor industry with a number of job assignments in USA, Asia and Latin America. He is currently the Strategic Packaging Research and External Collaborations Manager at Texas Instruments packaging organization. This organization is responsible for researching new, path finding packaging technology for TI.

His contributions to the industry have been recognized with several national level professional and technology awards.

Invited key note speaker in multiple international packaging conferences; published several technical papers in journals and technical magazines, and co-authored a chapter in an electrical engineering text book.

Author of ten U.S. patents for Packaging technology related to the development and introduction of new assembly equipment and processes.

Sesh Ramaswami
Senior Director, Strategy
Silicon Systems Group
Applied Materials Inc.

Sesh Ramaswami is Sr. Director, Strategy in the Silicon Systems Group at Applied Materials. In this capacity, his responsibilities include program definition and execution, defining and driving external collaboration and co-leading internal process integration programs for the TSV initiative.

Sesh has over 25 years of semiconductor industry experience. Over the past 15 years at Applied Materials, he has had varied technical and business experience in product management and product development and advanced materials development. Prior to joining Applied Materials in 1994, Sesh had thin film process development responsibilities at Advanced Micro Devices and at National Semiconductor. A holder of 35 US patents and several publications, Sesh has undergraduate and graduate degrees in Chemical Engineering from Indian Institute of Technology, Kanpur, and Syracuse University respectively and a MBA from San Jose State University. He may be contacted at Sesh_Ramaswami@amat.com

Subramanian Iyer
Distinquished Engineer at IBM Systems & Technology Group
IBM