Managing the New Economics of
Semiconductor Manufacturing
Monday, May 16, 8:00-8:45AM
Japan: The Long Road Back
Keynote Speaker:
Keenan Evans
Sr. VP of Quality, Reliability & EHS
ON Semiconductor
As the events of March 11 unfolded it immediately became apparent that our reaction would need to escalate rapidly from local emergency response to crisis management, to business continuity and ultimately to nation rebuilding.
As with all other impacted entities the ON Semiconductor initial focus was on the safety and well being of our people. Local emergency response teams with the assistance of the global corporate crisis management team quickly ascertained that all of our employees were safe and unharmed. Assessment of the physical damage to our facilities and to the local infrastructure soon followed. Then came the tasks of repairing any damage, returning the facilities to a safe and operable condition, rebuilding the supply chain and resuming production.
With approximately 6,000 employees and multiple factories operating in the region the impact on the continuity of supply to our customers could potentially be quite significant if we did not react rapidly to recover. We also had to be mindful of our responsibility to assist with massive humanitarian efforts necessary to provide relief to the most impacted regions. This talk will cover the reaction, assessment and recovery process from the perspective of the corporate executive sponsor and team leader of crisis management and business continuity planning.
Keenan Evans is currently the Senior Vice President for Quality, Reliability & EHS for ON Semiconductor. In addition to his titular duties he serves as the executive sponsor for the corporate cross functional teams responsible for crisis management, business continuity and corporate social responsibility. Keenan has a 30 year history in the semiconductor industry and has held a number of different technical and managerial positions including technology director, materials analysis, device and process development, quality, reliability and EHS. Dr. Evans received his Ph. D. and BS in chemistry both from Arizona State University in 1981 and 1977, respectively.
Monday May 16, 8:45 – 11:00 AM
SESSION 1- Defining the New Semiconductor Landscape: a
Post-Recession Look at the State of the Industry
The session will cover the industry’s dramatic recovery in 2010 and a continued positive outlook for 2011 and 2012; the impact of consumerization, where almost 60% of semiconductor sales are driven by consumer demand; the restructuring of the industry that may leave only a handful of companies with the financial and technical resources to produce devices at the very leading edge; and the long term outlook for a maturing, yet-still-cyclical industry (cyclicality is a function of supply and demand, capacity, average selling price, and the high capital and operating costs of a fab).
Session Leader:
Paul Edstrom
CTO, GE Commercial Finance
Global Electronics Solutions
Paul Edstrom is responsible for the development and management of GES' lease portfolio, and all product management and strategic OEM alliances. These responsibilities encompass IC manufacturing, ATE, printed circuit board assembly, and FPD equipment segments. A 27-year industry veteran, Edstrom began his career with Intel Corporation in Santa Clara and then moved to Ultratech Stepper. Most recently, Edstrom served as a founding member and senior vice president of Comdisco Electronics Group, where he was responsible for strategic alliances and product management.
Speakers:
Bob Krakauer
CFO
GLOBLFOUNDRIES
Taking the Long View: A Strategic Approach to Investment in Semiconductor Manufacturing
On the heels of a historic recession in 2009 and a recovery of unprecedented proportions in 2010, the coming years raise a number of serious questions for leaders in the semiconductor industry. Are we building too much capacity and risking a potential glut, or are we not investing enough to keep up with skyrocketing demand? How can we continue the march of technology scaling, while simultaneously managing complex and expensive transitions to next-generation lithography and 450mm wafers? Can we count on the fast-growing market for smart mobile devices to continue driving demand for leading-edge silicon? And perhaps most importantly, how many companies will be able to remain competitive in this cyclical, unpredictable, and incredibly capital-intensive industry? There are no easy answers, but one thing is for certain: semiconductor manufacturers need to take a long-range perspective. Over the long term, the growth will be there, especially in terms of advanced technologies. With each new product, consumers are expecting more from their smart mobile devices, including PC-class performance, extended battery life, highly integrated multimedia experience, and full-featured web capabilities. To meet these expectations, designers must turn to more advanced semiconductor technology. At the same time, the IDM business model is becoming less attractive as the cost of maintaining advanced manufacturing capabilities grows exponentially. IDM outsourcing will continue, especially at the leading edge. These factors make it clear that the only manufacturers that will stay competitive at the leading edge will be those with the resources and vision to take a strategic, long-term approach to investment.
Bob Krakauer is Chief Financial Officer at GLOBALFOUNDRIES. Krakauer joined GLOBALFOUNDRIES as CFO in August 2010 and is responsible for the company's overall financial management, reporting and strategy, and financial analysis functions.
Prior to joining GLOBALFOUNDRIES, Krakauer served as Chief Financial Officer at LifeLock where he was responsible for improving it's internal control structure, developing financial practices that helped improve execution, and creating financial and accounting systems that facilitated the company's growth.
Prior to LifeLock, Krakauer served as President and CFO for MagnaChip Semiconductor in Seoul, Korea and served as the Executive Vice President of Corporate Operations and Chief Financial Officer for Chippac, Inc., which he helped take public on NASDAQ. Krakauer has also held executive leadership roles in finance and business development for leading global technology companies, including AlliedSignal, Alphatec, and Altera.
Krakauer holds a bachelor's degree in accounting and a master's degree in business administration from Santa Clara University where he is currently a member of the business school's advisory board. 
Harvey Frye
Vice Chairman
Tokyo Electron America
Defining the New Supplier Landscape- Parallel IC & Supply Chain Universe
As a presenter in the general session, entitled “Defining the New Semiconductor Landscape”, Harvey will start with a brief look at the history and key drivers of how equipment and process have evolved (1970 – 2010), as well as the shifting roles and responsibilities. TEL’s evolution will be used as a case in point.
Looking forward, numerous decreasing and increasing key factors will be highlighted and then inserted into a business model progression roadmap and discussion that leads to the future. This will map into the micro-electronic ecosystem needs with parallel and overlapping implications for all participants. Rationale will be explained, as well as some examples of how TEL is evolving to serve this dynamic continuum of growing parallelisms.
Mr. Frye has been Vice Chairman, Tokyo Electron America since October of 2009. In this role he is currently focused on contributing to TEL’s corporate business strategy in the solar/energy sectors, as well as oversight of US Micro-electronics customer relations, and various other projects.
Prior to this role he was President of TEL America from 2004-2009, focusing on TEL’s sales and support operations for North America. Before being President he was the Senior VP of Marketing, Sales and Service. Mr. Frye joined TEL in 1998.
He has been a sales, marketing and field operations executive in the semiconductor industry for 30 years with Eaton Corp., KLA Instruments, and a startup company assisting with the IPO and a later merger. Preceding the semiconductor industry tenure, he had other industry experience in marketing and manufacturing management.
Mr. Frye earned a B.S. degree from the University of New Hampshire in 1974.
He currently serves on the Austin Technology Council Board of Directors and various advisory boards; including SEMI North America, University of Texas at Austin’s College of Natural Science Foundation, Memorial Museum/Natural Science Center, and ATI Clean Energy Incubator.
Robert Bruck
VP Technology & Manufacturing Group
General Manager, Technology Manufacturing Engineering
Intel
Defining the New Semiconductor Landscape: A Post-recession Look at the State of the Industry
The Semiconductor industry has reached a strategic inflection point with unprecedented challenges and opportunities. With the rapid expansion of the computing continuum, consumers and emerging markets are driving an enormous increase in the number of devices connecting and sharing information through a rapidly expanding network and a central cloud structure, which will require sustained investment over many years to keep up with network capacity requirements. Investments in R&D and capital are climbing rapidly to support the roadmap for software, design, process technology development and new packaging form factors. These investments require expanding economies of scale to provide cost effective solutions for consumers. This scale expansion is driving consolidation and new business models at many level s of the value chain. To meet the dual challenges of R&D investments and capital intensity, new forms of collaboration and industry cooperation are emerging to ensure long term growth and success of industry participants.
Robert E. Bruck is vice president of the Technology and Manufacturing Group and general manager of the Technology Manufacturing Engineering (TME) organization. In this role, Bruck is responsible for managing semiconductor equipment industry relations, including development and delivery of equipment capabilities to meet Intel process technology and manufacturing roadmaps, supply chain capacity management, capital affordability, asset utilization and conversion capabilities, equipment maintenance and technical training.
Bruck holds a bachelor's degree in marketing and a masters degree in business administration with a concentration in finance from Arizona State University.
Ivo Bolsens
Senior VP & CTO
Xilinx
Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP).
Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven in Belgium
Monday May 16, 1:45 - 3:15
SESSION 2-Collaboration to Strengthen the IC Supply Chain:
As the IC industry continues to scale to smaller dimensions and higher complexity chips – often called More Moore -- we’ll face increased DPI (design/process interaction) and CPI (chip/packaging interaction) challenges. This will require stronger interactions among fabless, foundry and packaging companies. On the other hand, moving to “More than Moore” such as 3D TSV, we will see more integration issues including KGD (Known Good Die) on interposer or 3D stacking, wafer thinning/handling, and heterogeneous 2D or 3D integration of chips. The supply chain will become much more complicated as additional interfaces will have to be managed. Since our IC industry has long been divided into EDA or fab tool supplier, fabless, foundry and assembly/test companies, getting everyone work together and making profit for each party can be extremely challenging. This session is intended to explore various alternatives.
Session Leaders:
John Chen
VP of Technology and Foundry Operations
Nvidia
Dr. Chen has 30 years of experience in IC industry ranging from IDM to Foundry to Fabless companies. He started his career as a researcher in Hughes Research Laboratories, subsequently at Xerox Palo Alto Research Center (PARC). Most of his work involves CMOS devices and process technologies. Later, he has had various technical and managerial positions in technology development and IC manufacturing. He was the Director of Technology Development at Cypress Semiconductor.
Dr. Chen was a Howard Hughes Doctor Fellow and received a Ph.D. in EE and an Executive Management degree, both from UCLA. He also holds a M.S. from University of Maine and a B.S. from National Taiwan University, both in E.E.
Jeong-ki Min
VP of Foundry Marketing
Samsung Electronics Co., Ltd.
Jeong-ki Min is a vice president of Foundry Marketing at Samsung Electronics’ System LSI Division. Since 1984 when he joined Samsung, Mr. Min has worked in various functions ranging from marketing, technology planning, and capital investment to M&A and other strategic alliances. He also worked for Samsung’s US operation located in San Jose, California, as a planning officer.
Throughout the years he worked for Samsung, Mr. Min leads Foundry and ASIC Marketing team and his current responsibility at System LSI Division includes Business development and Market research and Customer engineering supports
Abraham Yee
Director Advanced Technology & Package Development
Nvidia Corporation
Abe Yee is currently Director of Advanced Technology and Package Development at NVIDIA Corporation, responsible for readying next generation technologies for production, benchmarking technologies, investigating new technologies and setting NVIDIA's process roadmap. Prior to NVIDIA he was Director of Engineering at SUN Microsystems responsible for SPARC processor production, VP of Operations at Equator technologies, and Director at LSI Logic Corp, where he was responsible for technology development. Dr. Yee received his BA in Mathematics and Physics and his PhD in Physics from UC Berkeley. Dr. Yee received his BA in Mathematics and Physics and his PhD in Physics from UC Berkeley.
Speakers:
John Waite
VP, Packaging Development
& Central Engineering
GLOBALFOUNDRIES
Supply Chain Reaction: A Collaborative Approach to Packaging Innovation
As the industry moves aggressively to more advanced technology nodes, innovation in interconnect, assembly and packaging solutions is becoming increasingly critical. This once “bland” aspect of the supply chain has become a hot topic, as the ability to enable innovative packaging techniques can lead to improvements in performance and power-efficiency as well as reduced costs for chip designers. As packaging continues its evolution, the complexity of chip-package interaction (CPI) is going up significantly and there is an increasing need for coordination between design and manufacturing to ensure that foundry wafers can support designers’ needs. Different end-products drive a variety of considerations in packaging, depending on the need for performance, cost-efficiency, or small form factor. It is increasingly difficult for foundries and OSATs to be able to deliver end-to-end solutions that meet the requirements of this range of leading-edge designs. A new approach is needed—one that leverages the success of the “shared investment, shared return” model that has accelerated innovation in the world of process technology. On advanced silicon nodes, foundries need to engage early with OSAT partners to jointly develop packaging solutions for customers, developing a broad and open ecosystem where customers have maximum choice and flexibility. This approach can lead to resource efficiencies, cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.
John Waite is Vice President of Packaging Technology Development and Central Engineering at GLOBALFOUNDRIES. In this role he is responsible for global packaging development, collaborative R&D activities with partners and customers. He has additional responsibilities in a wide area of central engineering supporting technology development at GLOBALFOUNDRIES.
Waite joined GLOBALFOUNDRIES in 2009 after a 25-year career in technical and management positions at AMD and IBM. Immediately prior to joining GLOBALFOUNDRIES, Waite served as Vice President of Enterprise Supply Management at AMD , where he was responsible for the integration of ATI’s fabless supply chain with the classic AMD IDM model. At IBM, Waite held semiconductor technical and leadership positions, in development, operations, supply chain and business development.
Raj Pendse
VP Product & Technology Marketing
STATS ChipPAC
3D Packaging Evolution from an OSAT Perspective
The drivers for 3D Si integration based on device and system architecture are reviewed. The resulting evolution of packaging technology and it’s logical mapping into 3D TSV approaches is presented. The synergies and intersections among parallel developments in the three areas of packaging technology i.e. traditional die and pkg stacking on substrates, fan-in and fan-out wafer level packaging and 3D Si integration and the resulting future path for packaging technology is illustrated. The transformed role of the OSAT industry in supporting the above evolution is explained. Latest developments in the key elements of 3D Si integration such as wafer thinning, micro bumping, micro bonding and logical hand off points among Si and package foundries are presented. The status of “bridge” technologies such as interposers and TSV substrates as an interim play prior to full productization of the active Si TSV approach is reviewed with specific examples of configurations approaching volume production in real products.
Dr. Raj Pendse is Vice President of Advanced Products and Technology Marketing at STATS ChipPAC. Prior to joining STATS ChipPAC, Raj held various positions in package engineering and R&D at National Semiconductor Corp and Hewlett-Packard Labs. His work has spanned the gamut from packaging of high-end microprocessors, ASIC and graphics products to low-cost packaging solutions for logic and analog devices that find use in mobile phones and consumer products. His most recent focus has been on Flip Chip and 3D Wafer level packaging.
Raj completed his BS in Materials Science from IIT Bombay with Top in Class honors and his Doctorate in Materials Science from UC Berkeley.
Robert Darveaux
CTO
Amkor
Supply Chain Challenges for 3D Integration of Memory and Logic Devices using TSVs
The Package-on-Package (POP) platform has proven to be a very successful format to achieve 3D integration of logic and memory devices in high volume applications. The key elements of POP technology that have enabled this success include: each component can be tested and burned in separately; there is no margin stacking because each component is sourced separately by the OEM or EMS provider; the joining technology is widely available; the joining process is very high yielding; and there is relatively clear ownership of defect liability.
Integration of memory and logic devices using through silicon vias (TSVs) is not yet mature, so most of the favorable attributes of the POP business model are not yet developed. The following state exists: Very high density area array contact pads or bumps are difficult to probe test; bare or partially assembled memory and logic die are difficult to burn in adequately; the joining technology is not widely available to OEMs and EMS providers (hence, the current business model which prevents margin stacking might not be available); the joining process yield is not well characterized; and due to the immaturity of the test, burn-in, and assembly there might be no clear ownership of defect liability.
The industry needs some innovative test and inspection technologies. Creative business models and partnerships need to be formed. More cycles of learning with higher volumes of samples are required to gain confidence in joining process yields. More reliability data needs to be gathered to establish baseline performance and product robustness.
Robert Darveaux is Corporate Technology Officer at Amkor Technology. Robert has 24 years experience in the IC packaging field at the Microelectronics Center of North Carolina, Motorola, and Amkor. Robert has a B.S. in Nuclear Engineering from Iowa State University and a Ph.D. in Materials Science and Engineering from North Carolina State University. His areas of expertise in IC packaging include thermal and mechanical simulation, materials characterization, failure analysis, and fatigue life prediction for solder joints. Robert has published over 75 technical papers and has 22 patents.
Nick Yu
VP of Technology Development
Qualcomm
3D Through Si Stacking Technology - a Qualcomm Perspective
An overview of the Qualcomm perspective on 3D through-Si-via based stacking technologies is given, and an outline of the primary motivations for Qualcomm’s interest in this technology is summarized . A roadmap for the evolution of the 3D technology is proposed, and the integration challenges for an Integrated Fabless Manufacturer using a distributed supply chain are outlined. Qualcomm’s implementation strategy is described, and a snapshot of the status of the industry-wide activities, such as the efforts to create standard, is provided. The current key issues are highlighted and some of the gaps in the business model associated with 3D products are discussed.
Nick Yu is a Vice President of Engineering at Qualcomm’s CDMA Technologies Division. He is currently responsible for setting Qualcomm’s semiconductor technology roadmaps including wafer fab process node, backend interconnect and packaging technologies. He manages engineering teams that are involved with our supply chain partners on execution of the technology roadmaps for Qualcomm’s chipset products. Nick has 18 years of experience with Qualcomm on low power wireless chipset and SoC development, including managing chipset design, advanced semiconductor technology, deep submicron circuit design and methodology development, advanced semiconductor R&D and packaging development. He is one of the architects of, and has participated in the definition and development of, many Qualcomm chipset products. Nick has an MSEE degree from Georgia Institute of Technology
Tuesday, May 17, 8:00-8:45AM
Keynote Speaker:
Bill McClean
President
IC Insights
IC Industry Growth Momentum
There is no doubt that supply will be constrained in numerous areas relating to the electronic system and semiconductor industries due to the earthquake and tsunami in Japan. However, on a worldwide basis, IC Insights believes that demand for electronic systems and semiconductors will only be slightly lessened due to this disaster. Moreover, any lessening of system or semiconductor demand in 2011 due to the earthquake is forecast to be delayed and pushed into 2012, but not destroyed.
In terms of the supply chain, it should be kept in mind that one company’s misfortune is another’s opportunity. Whether it is automobiles, electronic systems, silicon wafers, or flash memory, other suppliers worldwide will be aggressively attempting to make up for any shortfall in supply coming out of Japan this year. While it is not easy to switch suppliers of key products, businesses will always eventually find a way to continue to move forward.
Mr. McClean began his market research career in the integrated circuit industry in 1980 and founded IC Insights in 1997. During his 31 years of tracking the IC industry, Mr. McClean has specialized in market and technology trend forecasting and was responsible for developing the IC industry cycle model. At IC Insights, he serves as managing editor of the company’s market research studies and reports. In addition, he instructs for IC Insights’ seminars and has been a guest speaker at many important annual conferences held worldwide (e.g., SEMI’s ISS and Electronic Materials Conferences, The China Electronics Conference, and The European Microelectronics Summit). Mr. McClean received his Bachelor of Science degree in Marketing and an Associate degree in Aviation from the University of Illinois.
Tuesday, May 17, 8:45 - 10:15AM
SESSION 3-The Challenges of Continued Scaling:
This session will look at critical technologies required to remain on the path defined by Moore’s Law. Presenters will emphasize the present status and cost of development, including next generation lithography (and the rise of computational lithography), the transition to 450mm wafers, which appears to be finally underway, and front-end issues related to transistor formation – most notably the use of high-k metal gates and strained silicon – and on-chip interconnects.
Session Leaders:
Hans Stork
CTO
ON Semiconductor
Hans Stork is the Chief Technology Officer (CTO) and senior vice president for ON Semiconductor, a premier supplier of high performance silicon solutions for energy efficient electronics Under Dr. Stork’s leadership, ON Semiconductor will focus its organic research and development (R&D) and technical innovation to further expand the company’s energy efficient product and solution offerings in key market segments including computing, consumer, LED lighting, smart grid, automotive and wireless applications.
Dr. Stork joins ON Semiconductor after three years with Applied Materials as Group Vice President of the Si Systems Group and six years with Texas Instruments as the company's CTO and Senior Vice President of Si Technology Development. He has close to three decades of experience in technology, product development and leadership management areas. During his career Dr. Stork has worked with some of the semiconductor industry’s leading innovators including Hewlett Packard and IBM Research.
Dr. Stork holds a PhD in Electrical Engineering from Stanford University, and an Electrical Engineering Ingenieur (Cum Laude) from Delft University in the Netherlands. He has authored numerous scientific articles and papers, and served as a board director for Sematech and the Semiconductor Research Corporation (SRC) and is a member of the Scientific Advisory Board for IMEC.
Janice Golda
Director, Lithography Capital Equipment Development
Intel
Janice Golda manages an organization responsible for creating strategies and working with Intel’s lithography, mask, and metrology suppliers and sub-suppliers to deliver equipment meeting Intel’s roadmap technology, capacity, and cost requirements. She has represented Intel on the SEMATECH Lithography Program Advisory Group, the US Lithography Technical Working Group, and the International EUV Symposium, and has presented and published for numerous industry forums. Janice is a member of the Berkeley CXRO Advisory committee and is Chairman of the Board for the EUV LLC. She holds one US patent. Janice joined Intel in 1989 and has held positions in lithography process engineering and program management. Janice earned a BS degree in Electrical Engineering from Cornell University.
Paul Farrar
VP Albany Expansion and Strategic Initiatives
IBM
Mr. Farrar has 32 years experience in the Semiconductor Industry. He is currently Vice President for Albany Expansion, a role he was appointed to in March 2010. He is responsible for Joint Development Alliances and the growth of the Albany Eco System and IBM’s Collaborative Model. In addition, he is responsible for managing the capital budget for the Microelectronics Division. He is also on the governing board of CCNI, a super-computer partnership between New York State, IBM and Rensselaer Polytechnic Institute.
For the past seven years, he was Vice President for Semiconductor Process Development at IBM. In this role, he managed 700 IBM and partner Research and Development engineers and scientists and was responsible for Unit Process, Lithography and Characterization. Previously, he held numerous positions at IBM in Manufacturing and Development. Mr. Farrar managed IBM’s Semiconductor Fab in Burlington, Vermont; managed IBM’s SRAM and DRAM businesses and has spent the last seven years in Process Development. In addition, he has negotiated numerous strategic alliances with semiconductor equipment manufacturers and IDM’s. Mr. Farrar has a B.S. and M.S. in Materials Engineering from Rensselaer Polytechnic Institute.
Speakers:
Thomas Jefferson
450mm Program Manager
ISMI
450mm: Progress, Plans, and Strategy
Increasing wafer size has historically been a successful strategy to offset rising costs of leading-edge semiconductor manufacturing. ISMI, its members, and partners have defined fundamental pre-competitive 450mm infrastructure and guidelines, and momentum towards realization of the 450mm transition is strong in all areas of the semiconductor manufacturing supply chain. ISMI is currently working to enable 450mm equipment development by providing bare and processed silicon, and metrology capabilities, with a goal of demonstration of unit-process capability and equipment reliability to support device maker 450m pilot line startups. A comprehensive overview of the current state of the 450mm landscape will be provided, along with the case for industry collaboration to enable a cost effective wafer size transition.
Tom Jefferson is Program Manager of 450mm Transition at International SEMATECH Manufacturing Initiative (ISMI). He has been on assignment from Intel Corporation since June 2008. Over the past three years he has led all aspects of ISMI’s 450mm transition planning effort. Prior to his assignment at ISMI, Jefferson held various managerial and technical positions in the areas of factory automation, factory integration, systems engineering, wafer size conversion, industrial engineering, and material handling. He is formally the co-chair of the ITRS Factory Integration technical working group, and a former member of the ASMC technical committee. Jefferson holds a BS in industrial engineering from the Rochester Institute of Technology (RIT). He is the author of 20 publications in his areas of technical expertise.
Dave Medeiros
Director of Patterning
IBM
Lithography Challenges for the Next Decade
While EUV has made significant strides recently, there still remains a gap of at least a few years until this technology reaches maturation for high volume manufacturing readiness. Faced with a plateau in the tooling capabilities of optical lithography from both wavelength and numerical aperture after the implementation of water based immersion ArF technology, researchers have further extended the scaling roadmap by innovations in materials, process controls and computational methods. While Double Patterning Lithography (DPL) will bridge the gap until EUV is fully realized, there are debatable limits to how extensible this technology is. It has been demonstrated that DPL can afford resolution requirements of next node technologies, albeit at increased complexity and cost and with both increasingly tighter process window budgets and design restrictions. Understanding the tradeoffs between these disparate considerations and the opportunities afforded by new materials and computational solutions are challenges the lithography community faces with as we progress toward the edge of optical lithography capability.
David Medeiros is the Director of Patterning Solutions at IBM’s Semiconductor Research and Development Center in East Fishkill, NY. He joined IBM in 1998 after receiving his Ph.D. in Organic Chemistry from the University of Texas in Austin. Previously he was employed by the Shipley Company (now Dow Electronics Materials) in Marlborough, MA for 6 years as a synthetic chemist. He received a BS in Chemistry from the University of Massachusetts, Amherst in 1988. He is the author of numerous publications in the areas of lithography, materials science and semiconductor processing. He holds in excess of fifty US issued patents and has been named an IBM Master Inventor. He lives in the Berkshires of Western Massachusetts with his family.
Raj Jammy
VP Materials & Emerging Technologies
SEMATECH
Raj Jammy received his doctoral degree in Electrical Engineering from Northwestern University (1996). He joined IBM’s Semiconductor Research and Development Center in East Fishkill, NY, where he worked on various aspects of DRAM technology development in engineering and managerial roles. In 2002 he moved to IBM T. J. Watson Research Center in Yorktown Heights, NY, to manage IBM’s efforts on high k gate dielectrics and metal gates. From 2005 to 2008 he was an IBM assignee to SEMATECH as the Director of the Front End Processes Division. He is currently the Vice President of Materials and Emerging Technologies at SEMAETCH, with responsibilities in advanced logic, memory, 3D interconnects and emerging device technologies. He holds more than 50 patents and is an author/co-author of over 200 publications/presentations.
An Steegen
SVP for Integration
IMEC, Belgium
Tomorrow’s smart systems will require extreme computation and storage capabilities, orders of magnitude above what processors and memories of today can deliver. There is thus a need to keep on scaling technology. For more than 10 years now, transistor scaling is considered to have reached its limits. But we have always found new solutions. To get to ultra-small dimensions beyond 10nm, we have to use new materials such as high-mobility Ge and IIIV materials. And we have to look into new device architectures such as FinFETs and TunnelFETs with heterojunctions. Moreover, 3D stacking will allow even more functionality, computing power and memory on-chip. Also new memory concepts such as Resistive RAM, floating-body RAM and vertical Flash memory are arising to further reduce the cost and maximize the memory density as required by the emerging high-end applications.
Looking at the lithography landscape, there are two persisting trends. EUV lithography is slowly maturing towards production-ready tools. Before that, 193nm immersion lithography is inching nanometer per nanometer past all limits that we thought insurmountable just a few years ago.
Dr. An Steegen joined IMEC as Senior Vice President Process Technology Development in December 2010. In this role, she has the responsibility for the technical leadership and execution of IMEC’s CORE Program activities in the areas of devices, process, lithography and design and CMORE activities such as MEMS, Power, Sensors and Photonics. These leadership technologies serve as the foundation of IMEC’s successful growth and R&D leadership position in a wide variety of market segments.
Dr. An Steegen holds a Ph.D in Material Science and Electrical Engineering from the Catholic University of Leuven, KUL, in collaboration with the Interuniversity Microelectronics Center, IMEC, in Belgium. Throughout the years, Dr. Steegen has published more than 30 technical papers and she holds many patents in the field of semiconductor development. She joined IBM Semiconductor R&D in Fishkill, NY, in 2001, where she was the director of the Bulk CMOS Technology Development division until 2010. In that position, she served as the host executive in charge of IBM’s logic International Semiconductor Development Alliance and was responsible for establishing strong collaborative partnerships in innovation and manufacturing as measured by power/performance, defect density and cost/complexity.
Tuesday May 17, 2:45 - 3:45 PM
SESSION 4 -Panel Session: Bridging the Fabless-Foundry Gap
A key trend in the semiconductor industry is a shift from internal chip manufacturing capabilities to fabless and fab-lite or asset-lite models. Companies such as Nvidia, Qualcomm and Broadcomm have seen great success by designing chips and outsourcing the manufacturing to foundries such as TSMC, UMC and Global Foundries. This move to fabless has been going on for some time, but what’s changed is that fabless companies are pushing foundries, as well and equipment and materials suppliers, to develop new capabilities to address their unique requirements. This panel session is designed to give fabless companies and foundries a forum to describe what they would like see developed and discuss how to better collaborate.
Session Leaders:
John Lin
Director of Mfg Technology Center
TSMC
John Lin received his PH. D. degree in Opto-Electronic Engineering from University of Oxford in 1994. He has worked on semiconductor technology development in Industrial Technology Research Institute, Taiwan and then in Vanguard International Semiconductor Corporation from 1994 to 1998.
He joined Taiwan Semiconductor Manufacturing Company as a department manager of mask technology on Oct. 1998 and later in lithography technology development through 0.25um down to 45nm. Since Feb. 2006,
He has been the Director of Manufacturing Technology Center.
John has given a few invited talks at "Immersion Lithography", and "450mm Wafer Strategy“, and issued 40 US patents, author or co-author of 25 technical papers. He also awarded to the National Excellent Young Engineer in 2004 and the National Outstanding Engineer in 2008 by the Chinese Institute of Engineers.
Geoffery Yeap
VP of Technology
Qualcomm Inc.
Dr. Geoffrey Yeap received BSEE, MSEE and Ph.D. in Electrical & Computer Engineering specializing in Microelectronics from The University of Texas at Austin. He has twenty years of semiconductor experience working at Univ of Texas System Supercomputing Center, AMD, Motorola and Qualcomm in microprocessor and wireless silicon technology research & development, new technology/product introduction/manufacturing, and design/technology optimization.
He is an IEEE senior member, and holds >25 US/international patents, and publishes more than 75 referral jornal and conference papers. He serve as a member of VLSI Technology commeetee and IEDM 2001-2002 Integrated Circuits & Manufacturing and 2009-2010 CMOS Tech/Device sub-committees, and SIA ITRS Process Integration & Device Structures Technical Working Group. . He is currently a VP of Technology at QCOM in charge of all the silicon technology (digital, RF, analog and high voltage etc) and foundry IP/design enablement
Speakers:
BJ Woo
Sr. Director Graphic/ PLD/CPU Business Development Division
TSMC
BJ Woo joined TSMC as Senior Director of Technology Roadmap Division in April 2009. She is currently in charge of the High Performance Technology definition for Graphic/PLD/CPU Business Development Division. Prior to joining TSMC, BJ has spent most of her career life in Intel Corp for 24+ years.
In the 1980’s, BJ concentrated on non-volatile technology development, and accumulated 13 patents for her work. In the 1990’s and early 2000’s, BJ shifted her focus into driving Intel’s microprocessor performance and cost, leading teams to push microprocessor GHz clock speed and new generation of silicon technology.
In 2002, BJ took a career excursion, and joined Grace Semiconductor in Shanghai as Vice President of technology development. She started from scratch and built a technology development organization in a brand new foundry.
In 2004, BJ moved back to the US and rejoined Intel as Director of technology integration and development, responsible for driving multiple leading edge non-volatile-memory technologies, and defining technology roadmap for NOR flash. Because of her excellent work and leadership, she was nominated by Intel and was honored as 2006 Hall of Fame for WITI (women-in-technology-international).
Paul Farrar
VP Albany Expansion & Strategic Initiatives
IBM
Mr. Farrar has 32 years experience in the Semiconductor Industry. He is currently Vice President for Albany Expansion, a role he was appointed to in March 2010. He is responsible for Joint Development Alliances and the growth of the Albany Eco System and IBM’s Collaborative Model. In addition, he is responsible for managing the capital budget for the Microelectronics Division. He is also on the governing board of CCNI, a super-computer partnership between New York State, IBM and Rensselaer Polytechnic Institute.
For the past seven years, he was Vice President for Semiconductor Process Development at IBM. In this role, he managed 700 IBM and partner Research and Development engineers and scientists and was responsible for Unit Process, Lithography and Characterization. Previously, he held numerous positions at IBM in Manufacturing and Development. Mr. Farrar managed IBM’s Semiconductor Fab in Burlington, Vermont; managed IBM’s SRAM and DRAM businesses and has spent the last seven years in Process Development. In addition, he has negotiated numerous strategic alliances with semiconductor equipment manufacturers and IDM’s. Mr. Farrar has a B.S. and M.S. in Materials Engineering from Rensselaer Polytechnic Institute.
Ming-yin Hao
VP of Field Application Engineering
UMC
Dr. Ming-yin Hao is Vice President of Field Application Engineering for UMC-USA. Before joining UMC US subsidiary, she was responsible for Technology Applications in UMC Taiwan Headquarter from 2001-2003. Prior to this role, she was the leader of 0.13um Process Integration at UMC Advanced Technology Development Center, and a core team member of UMC/IBM joint process development alliance.
Dr. Hao joined UMC after 5 years of service at AMD, where she worked on Logic Technology Development with the focus of CPU device architecture and performance/reliability optimization. She has over 25 journal and conference publications and holds 32 US/International patents.
Dr. Hao received her Ph.D. and M.S. degrees in Electrical Engineering from the University of Texas at Austin, and the B.S. degree from Electrical Engineering, National Taiwan University.
Mike Campbell
Senior VP of Engineering
Qualcomm
Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, responsible for QCT Product and Test Engineering, Test Automation and Failure Analysis. Mike joined QCT in 1996 as a Staff Engineer/Manager and during the last 12 years, Mike has held increasingly higher levels of responsibility at Qualcomm. At Qualcomm, Mike has been responsible for a number of various groups, including Design Automation, Yield Optimization, Product Engineering, Test Engineering, and Foundry Semiconductor Analysis. Mike initiated development and chose to expand the Qualcomm Design Center in India. In his current role, he is working to optimize the infrastructure & engineering required to bring leading edge products to market by developing partnerships/processes to optimize design stability, yield and test time early in the product cycle. Prior to joining QUALCOMM, Mike was an engineer and manager at several semiconductor companies, including Mostek, INMOS and Honeywell. He holds a BSEE & CE from Clarkson University.
Wednesday May 18, 9:00 - 10:30 AM
SESSION 5- High Growth Markets: Challenges and Opportunities
Many companies are seeing tremendous growth in markets that are closely related to mainstream semiconductors, including solid state lighting (high brightness LEDs), MEMS, flexible displays and energy storage. This is true both on the part of semiconductor manufacturers/foundries and equipment and materials suppliers. This session will provide an analysis of key trends in each area.
Session Leaders:
Pete Singer
Editor
Solid State Technology
Peter Singer has been covering the semiconductor and related industries for more than 26 years. Now Editor-in-Chief of Small Times and Solid State Technology, he was previously with Semiconductor International. He has authored more than 200 articles on all aspects of semiconductor manufacturing and related industries, including optoelectronics, photonics and photovoltaics. He has a degree in electrical engineering from the University of Illinois, Champaign-Urbana.
Aubrey Tobey
President
ACT International
Aubrey C. Tobey is president of ACT International. Since 1987, ACT has provided consulting services in management and marketing of technology to semiconductor circuit, flat panel display, MEMS, nanostructures, and manufacturing equipment industries. Services include strategic market planning and implementation programs especially for entry into new markets; market research, product definition, product development planning; resource audits and management; investment and diversification opportunities analyses; export control and international trade; and technology and business forecasting.
From 1965 he has been intimately involved in the evolution of micro-lithography technologies for the manufacture of semiconductor devices and allied products. Mr. Tobey has authored numerous editorials, articles and technical papers on micro-lithography. His activities in the international semiconductor markets span 46 years.
Since 1998 he has been on the board of Rudolph Technologies Incorporated, a leading thin-film metrology systems manufacturer of metrology systems; has served on the boards of several public, private, and start-up companies; and the board of SEMI, 1980-1983. He served from 1998-2003 on the board of Chartered Semiconductor Manufacturing Ltd. in Singapore, a leading foundry supplying advanced devices to major device manufacturers and fabless customers in US, Japan, Europe, Taiwan, and Singapore. Chartered is now a part of GlobalFoundies. In 2010 he joined the board of Periodic Structures, Inc., a private company engaged in development of optical interference-assisted lithography systems.
Mr. Tobey received his BS in ME from Tufts University School of Engineering in 1948, and his MS in ME from the University of Connecticut in 1954.
Speakers:
Iain Black
VP WW Manufacturing Engineering,
Technology & Innovation
Philips Lumileds
Iain Black is responsible for the worldwide operations engineering functions at Philips Lumileds, including NPI, sustaining operations, design for manufacturability and product/technology innovation across manufacturing sites in San Jose, Singapore, Penang and Maarheeze in NL.
In his 25yr career he has worked in a range of process engineering and manufacturing roles within the semiconductor industry in the UK, at INMOS Ltd, National Semiconductor, for the last 10 years he has lived in the US working in compound semiconductors at Anadigics and Philips Lumileds.
At Anadigics he was engaged in the creation of the first 6” GaAs RF manufacturing wafer Fab, the introduction of the first BiFET RF process into manufacturing and the construction of the first RF GaAs Fab in mainland China. He has now served for over 2 yrs in the LED space at Lumileds, running the SJ MOCVD Epi manufacturing operation, introducing the industries first 6” HB LED manufacturing capability, before taking on his current position in mid 2010.
Steve Wilcenski
President
MEMSCAP Inc.
Now that the novelty of Micro-electrical mechanical systems has worn off their benefit and utility can be best expressed by their ubiquity. Almost every component of modern communications and transportation incorporates MEMS devices at some level. These common applications have proven that MEMS are reliable, manufacturable and that they do provide the value that has been promised for so many years. While these high volume applications represent a very small number of potential uses for MEMS devices they account for the vast majority of today’s MEMS marketplace.
There are a number of other applications and markets prepared to embrace micromachines just as smart phones and automobiles have and new potential uses are emerging every day. With an overall projected MEMS market size rapidly approaching $100B for MEMS based systems the question is no longer will MEMS infiltrate technology at all levels but when, where and how.
Steve Wilcenski earned a B.S. in Materials Science and Engineering from North Carolina State University, an M.S. in Chemistry from Clemson University and an MBA from North Carolina State University. Steve’s current role as Vice President of the Custom Products Business Unit of MEMSCAP, SA / President of MEMSCAP, Inc., has successfully brought the CPBU to profitability in 2010. Steve has spent more than 10 years at MEMSCAP progressing through a variety of assignments beginning with process and product development and in leadership positions including Director of Business Development, Development Engineering Manager and Operations Manager. Prior to his time with MEMSCAP he held Engineering positions at Cree (Durham, NC) and Spectrolabs (Sylmar, CA). Steve is a guest speaker for the MBA program at NC State University and mentors engineering students from NC State.
David Icke
CEO
MC10 Inc.
Dave Icke joined MC10 as its founding CEO in March 2009. Before joining MC10, Dave spent almost twenty years in the semiconductor industry in marketing, process and product development, applications, and general management roles with Cypress Semiconductor, KLA-Tencor, and Teradyne. While at Teradyne, a leading supplier of automated test equipment, Dave ran the Wireless and Consumer Business Units within the Semiconductor Test Division, with responsibility for annual sales of up to $500M. Before Teradyne, Dave held a series of customer-focused roles over eleven years with KLA-Tencor, the leading supplier of process control solutions for semiconductor manufacturing, including VP of Marketing for the Wafer Inspection Division, KLA-Tencor's largest business. He began his professional career at Cypress Semiconductor as a lithography Process Development Engineer.
Dave also spent three years commercializing breakthrough technology with Advanced Electron Beams, a venture-backed startup providing a clean, efficient form of energy for industrial processing to the pharmaceutical, medical device, and beverage industries.
Dave has a passion for building great teams, commercializing innovative technologies, and introducing new products that enable customers to change the way they do business. Dave has a B.S. degree in Chemical Engineering from Stanford University, and an M.B.A. degree from Harvard Business School.
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